WDRESET=NORESET, WDEN=STOPPED, WDPROTECT=ANYTIME
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
| WDEN | Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. 0 (STOPPED): The watchdog timer is stopped. 1 (RUN): The watchdog timer is running. |
| WDRESET | Watchdog reset enable bit. This bit is Set Only. 0 (NORESET): A watchdog timeout will not cause a chip reset. 1 (RESET): A watchdog timeout will cause a chip reset. |
| WDTOF | Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. |
| WDINT | Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. |
| WDPROTECT | Watchdog update mode. This bit is Set Only. 0 (ANYTIME): The watchdog reload value (WDTC) can be changed at any time. 1 (LOWCOUNTER): The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |